PS/2 to USB wiring diagram
You may convert your PS/2 mouse/keyboard into USB. all you need is to modify cable wirings.
Cable Wiring Diagram
Keyboard PS/2 pinoutThe PC"s keyboard implements a bi-directional protocol. The keyboard
can send data (so called scan codes, unique for each button - one for
button pressed, another for button released) to the Host and the Host
can send data to the Keyboard. The keyboard is free to send data to the
host when both the KBD Data and KBD Clock lines are high (Idle). The
KBD Clock line can be used as a Clear to Send line. If the host takes
the KBD Clock line low, the keyboard will buffer any data until the KBD
Clock is released, ie goes high. Should the Host take the KBD Data line
low, then the keyboard will prepare to accept a command from the host.
The transmission of data in the forward direction, ie Keyboard to
Host is done with a frame of 11 bits. The first bit is a Start Bit
(Logic 0) followed by 8 data bits (LSB First), one Parity Bit (Odd
Parity) and a Stop Bit (Logic 1). The Keyboard will generate the clock,
typical frequency of the clock signal ranges from 20 to 30 Khz.
Pin Name Dir Description
|
1 | DATA | | Key Data |
2 | n/c | - | Not connected |
3 | GND | | Gnd |
4 | VCC | | Power , +5 VDC |
5 | CLK | | Clock |
6 | n/c | - | Not connected |
The keyboard and auxiliary device signals are driven by open-collector drivers pulled to 5Vdc through a pull-up resistor.Sink current Max: 20mA ;
Hi-level output V Min 5.0 Vdc minus pull-up ;
Low-level Output v Max 0.5 Vdc;
High-level input v Min 2.0 Vdc;
Low-level input v Max 0.8 Vdc.
PS2 ports use synchronous serial signals to communicate between the keyboard or mouse to the computer
Data transmission from the mouse to the
computer is done as in figure 1, each clock period is usually between
70 to 150 microseconds (10 to 25 microseconds for transitions and 30 to
50 microseconds for high or low state), some may feel that these are
large margins both this works good since this is a synchronous port
(this also helps cut on the cost of high precision clocks). The data
line transition is made on the falling edge of the clock signal and is
usually sampled when the clock is low. Each data packet is composed of
11 bits, 1 start bit (which is low), 8 data bits, 1 odd parity bit and
1 stop bit (high).
Pin Name Dir Description
|
1 | DATA | | Key Data |
2 | n/c | - | Not connected |
3 | GND | | Gnd |
4 | VCC | | Power , +5 VDC |
5 | CLK | | Clock |
6 | n/c | - | Not connected |
Note: Direction is Computer relative Mouse.